Today, packing several dies within one package is common knowledge. By packing different dies within one single mold, a package may provide increased functionality. It may also be possible to pack different application specific integrated circuits (ASIC) into one single mold cap to provide different functionality within one chip. However, increasing the number of dies results in increased package size within the stacked die packages. This may be a drawback when applying a stacked die package as bottom package in a package stack, as the clearance between the bottom package substrate and the top package substrate has to be large enough to have the bottom package dies and potential mold caps placed in between the substrates. In other words, the minimum distance between the substrates surfaces is limited by the thickness of the dies and mold cap of the lower package.
Stacked chip scale packages (stacked CSP) with two or more dies stacked within a single package assembly are known. These stacked packages may be organic packages, which are wire bonded and overmolded in a chip scale package profile.
A common approach for assembling stacked packages is to solder the top package, e.g. the substrate of the top package, on top of the bottom package. In particular solder balls at the edges of the substrates are provided. These solder balls allow soldering the top package on top of the bottom package. Typical ball pitch ranges from 0.5 to 0.8 mm for these packages. Also ball grid arrays using full-sized balls with only 0.5 mm maximum height are known. These chips are used in a surface down configuration. The size of the solder balls can also determine the ball pitch, e.g. the distance between the balls.
The typical limiting factor in package stack design can be, as previously pointed out, the clearance between the packages. To provide enough clearance between the packages, the size of the solder balls for soldering the top package on top of the bottom package is chosen to be larger than usual. However, larger solder ball sizes require larger pitch sizes, which again require larger substrate areas. For example, a pitch size of 0.65 mm can be required instead of 0.5 mm to take up all necessary connections between the top and the bottom package. This may increase the package stack size from 12×12 mm to 13×13 mm.
It has also been proposed to provide a hole in the substrate of the top package and to place the die of the top package through the hole on top of the mold cap of the bottom package, insofar as there is no substrate between the bottom mold cap and the top die. Available area for signal traces inside the substrate and available area for connecting elements is reduced, which may further increase package stack size and area requirement on the motherboard.
Other approaches provide placing the stacked dies on the top package. In this case, the lower package only comprises a single overmolded die and the top package comprises the stacked dies. However, the overall height of the stacked package pack is the same as placing the stacked dies within the lower package.
It has also been proposed to provide a hole in the substrate of the top package and to place the die of the top package through the hole on top of the mold of the bottom package, insofar as there is no substrate between the bottom mold and the top die. Available area for signal traces inside the substrate and available area for connecting elements is reduced, which may further increase package stack size and area requirement on the motherboard.
There is a need to reduce both the area and the height taken by packaging of chips. Further size reduction, in particular in terms of chip area, is also necessary. In addition, a further problem is to provide reliable multi-chip solutions even with low motherboard area and component height.